`timescale 1ns /100ps

module tagmem(clk, dataIn, dataOut,we, addr);
	input clk,we;
	input [6:0] addr;
	input [4:0] dataIn;
	output [4:0] dataOut;
	
	wire [4:0] dataOut;
	
	reg [4:0] core[127:0];
	
	always @(posedge clk)
		if (we) core[addr] <= dataIn;
	
	assign dataOut = core[addr];
endmodule

module bitmem(clk, rst, dataIn, dataOut, we, addr);
	input clk,rst,we;
	input [6:0] addr;
	input dataIn;
	output dataOut;
	
	wire dataOut;
	
	reg core[127:0];
	reg [7:0] i;
	
	always @(posedge rst)
		begin 
			i = 8'b0;
			while(i != 8'b10000000)
				begin
					core[i] = 0;
					i = i + 1;
				end
		end
	
	always @(posedge clk)
		begin
			if (we) core[addr] <= dataIn;
		end
	
	assign dataOut = core[addr]; 
endmodule

module tags(clk, rst, dataIn, dataOut, we, addr);
	input clk,rst,we;
	input [6:0] addr;
	input [6:0] dataIn;
	output [6:0] dataOut;
	
	wire [6:0] dataOut;
	
	tagmem tg(clk, dataIn[6:2], dataOut[6:2], we, addr);
	bitmem valid(clk, rst, dataIn[1], dataOut[1], we, addr);
	bitmem dirty(clk, 1'b0, dataIn[0], dataOut[0], we, addr);
	
endmodule